First Attempt at OpenSPARC SPC synthesis

My first attempt at OpenSPARC Single Processor Core (SPC) synthesis didn't succeed. Actually even the 2nd, 3rd and 4th attempt didn't succeed.

My first attempt was made on a 1GB computer in Digital Hardware Design (DHD) lab in Bharti Building. It gave an error issue with the memory. I switched over to a 3.3GB PC.

On that PC too, it gave some internal error. Now the problem I believe was this. We wanted to synthesize Single Processor Core and not T2 which would've included all the 8 cores. spc.v was a below t2.v source file when all the source files were added. But when I set spc.v as top module, I wasn't getting an option to synthesis in Xilinx ISE. But when I use to specify t2.v as the top module, only then did I get an option to synthesize. So my intuition says that it was trying to synthesize all the 8 cores. Why? Let us take a look at the script used to synthesize spc and t2.

$DV_ROOT/tools/fpga/fpga_synth -synplicity -top spc

$DV_ROOT/tools/fpga/fpga_synth -synplicity -top t2

i.e. only the top module is different for spc and for t2.

The file list needed to be added for both spc and t2 was located at:
$DV_ROOT/tools/fpga/fpga_synth

Therefore we reached a roadblock which we were unable to clear.

At the same time Mr. Ashish was trying to locate an open source toolkit chain. He came across one prospective Icarus Verilog, an open source verilog code synthesizer and simulator.