Chip Multithreaded (CMT) Processors
Historically, microprocessors have been designed to target desktop workloads, and as a result have focused on running a single thread as quickly as possible. Single thread performance is achieved in these processors by a combination of extremely deep pipelines and by executing multiple instructions in parallel (ILP)
The processor will be idle most of the time waiting on memory, and even when it is executing it will often be able to only utilize a small fraction of its wide execution width.
It is more efficient to have a number of small, single-issue processors (meaning it can only issue one instruction in a clock cycle) that employ multi threading built in the same chip area.
Combining multiple processors on a single chip with multiple strands per processor, allows very high performance for highly threaded commercial applications. This approach is called thread-level parallelism (TLP)
With processors capable of multiple GHz clocking, the performance bottleneck has shifted to the memory and I/O subsystems, and TLP has an obvious advantage over ILP for tolerating the large I/O and memory latency prevalent in commercial applications.
Historically, microprocessors have been designed to target desktop workloads, and as a result have focused on running a single thread as quickly as possible. Single thread performance is achieved in these processors by a combination of extremely deep pipelines and by executing multiple instructions in parallel (ILP)
The processor will be idle most of the time waiting on memory, and even when it is executing it will often be able to only utilize a small fraction of its wide execution width.
It is more efficient to have a number of small, single-issue processors (meaning it can only issue one instruction in a clock cycle) that employ multi threading built in the same chip area.
Combining multiple processors on a single chip with multiple strands per processor, allows very high performance for highly threaded commercial applications. This approach is called thread-level parallelism (TLP)
With processors capable of multiple GHz clocking, the performance bottleneck has shifted to the memory and I/O subsystems, and TLP has an obvious advantage over ILP for tolerating the large I/O and memory latency prevalent in commercial applications.
Source: OpenSPARC_Internals_Book OpenSPARCT2_Core_Micro_Arch
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