Simply RISC

As was mentioned in the earlier post, there were problems with synthesizing SPC of OpenSPARC. Also the following observations were made:

1. http://wienker.org/blog/?p=144 It is mentioned that it took 4.5 GB almost to synthesize a single core. With the current hardware available (3.3GB memory in the computer allotted to us), we cannot synthesize it.

2. http://fpga.sunsource.net/ It can be seen that the no. of LUTs required by SPC alone is about 60,000 which is pretty huge.

3. Instead of synthesizing SPC from SPARC's code, we can try working on SimplyRISC S1 core which is a cut down version of OpenSPARC T1, having just one core and importantly with ccx replaced by a wishbone.

http://en.wikipedia.org/wiki/S1_Core

http://www.srisc.com/?home

The cool thing about working with this is that it has been synthesized on Icarus Verilog Synthesizer. http://www.icarus.com/eda/verilog/ and the complete procedure is given on the developer's website.

http://news.techworld.com/operating-systems/6849/say-hello-to-open-source-hardware/

2. http://fpga.sunsource.net/ It can be seen that the no. of LUTs required by SPC alone is about 60,000 which is pretty huge.3. Instead of synthesizing SPC from SPARC's code, we can try working on SimplyRISC S1 core which is a cut down version of OpenSPARC T1, having just one core and importantly with ccx replaced by a wishbone. http://en.wikipedia.org/wiki/S1_Corehttp://www.srisc.com/?homeThe cool thing about working with this is that it has been synthesized on Icarus Verilog Synthesizer. http://www.icarus.com/eda/verilog/ and the complete procedure is given on the developer's website. http://news.techworld.com/operating-systems/6849/say-hello-to-open-source-hardware/">

We decided to work on synthesizing S1 core of Simply RISC. And after that we wished to extract FPU from T1/T2 and synthesize it alone.