Synthesis of S1 core (Simply RISC)

We decided to get working on synthesizing S1 core of Simply RISC. These were the steps I followed:

1. Install icarus-verilog from synaptic manager.
2. Extract http://www.srisc.com/download/s1_core.tar.gz
3. Read the specs http://www.srisc.com/download/simplyrisc-s1-0.1.pdf

Went to the folder in which s1 core was extracted.
In sourceme file made the following updation: export S1_ROOT=/home/aditya/SimplyRISC/s1_core

In terminal gave the following commands:

gedit sourceme
source sourceme
update_filelist
build_icarus
run_icarus
gtkwave /home/aditya/SimplyRISC/s1_core/run/sim/icarus/trace.vcd

and then from "File|Read Save File" choose the file named
"tools/src/gtkwave.sav".

Now it was time to synthesize it. I went through the same steps. After run_icarus I typed in fpga_build. But it gave the following error:

ERROR: Unable to read config file: /usr/lib/ivl/xnf.conf

: error: target_design entry point is missing.

error: Code generator failure: -2: error: target_design entry point is missing.error: Code generator failure: -2">

This was the same error at which Rudraksh was stuck. I thought this could be due to using icarus v 0.9.2 instead of 0.8 which the developers had used and I decided to install it from tarball. I also had to install flex and bison along the way. The error that I face has been logged in a text file here http://www.deorha.com/home/mtp/simply-risc . It is in errorlog_1

I decided to regress from gcc 4.4 to 4.1 due to an issue mentioned here:

http://osdir.com/ml/linux.debian.devel.ham/2007-12/msg00091.html

It didn't help.

Mr Ashish then suggested to modify build_fpga as:

iverilog -g1 -ss1_top -tnull -o fpga.edif -c$FILELIST_FPGA 2>&1 | tee synth.log

Synthesis worked after this but the synth.log was empty.

At this point it would be useful to check out http://iverilog.wikia.com/wiki/Iverilog_Flags

I replaced -tnull with -tfpga.

This time it asked for fpga.conf file instead of xnf.conf file. I downloaded icarus v0.9.2 and found fpga.conf file in it, but not present when icarus is installed from synaptic. I installed checkinstall, uninstalled icarus from synaptic and then installed icarus from source using checkinstall.

The same error repeated. Using sudo privileges I copied fpga.conf file from the source directory to /usr/local/lib/ivl. On copying strangely, fpga.conf file changed its form and it didn't open using gedit unlike earlier from the source directory. Its contents were:

functor:synth2
functor:synth
functor:syn-rules
functor:cprop
functor:nodangle
-t:dll
flag:DLL=fpga.tgt

I created a new file in /usr/lib/ivl and copied these contents in it and named it fpga.conf. Now when I ran the simulation it went one step further. But here is where I am stuck at today:

aditya@lira:~/SimplyRISC/s1_core$ build_fpga

/home/aditya/SimplyRISC/s1_core/hdl/rtl/s1_top/int_ctrl.v:47: sorry: Forgot to implement NetCondit::synth_sync

/home/aditya/SimplyRISC/s1_core/hdl/rtl/s1_top/int_ctrl.v:46: error: Unable to synthesize synchronous process.

/home/aditya/SimplyRISC/s1_core/hdl/rtl/s1_top/rst_ctrl.v:96: sorry: Forgot to implement NetCondit::synth_sync

/home/aditya/SimplyRISC/s1_core/hdl/rtl/s1_top/rst_ctrl.v:94: error: Unable to synthesize synchronous process.

/home/aditya/SimplyRISC/s1_core/hdl/rtl/s1_top/rst_ctrl.v:79: sorry: Forgot to implement NetCondit::synth_sync

/home/aditya/SimplyRISC/s1_core/hdl/rtl/s1_top/rst_ctrl.v:77: error: Unable to synthesize synchronous process.

/home/aditya/SimplyRISC/s1_core/hdl/rtl/s1_top/spc2wbm.v:162: sorry: Forgot to implement NetCondit::synth_sync

/home/aditya/SimplyRISC/s1_core/hdl/rtl/s1_top/spc2wbm.v:159: error: Unable to synthesize synchronous process.

:0: sorry: Forgot to implement NetBlock::synth_sync

/home/aditya/SimplyRISC/s1_core/hdl/rtl/sparc_core/cluster_header.v:335: error: Unable to synthesize synchronous process.

ivl: synth2.cc:212: virtual bool NetCase::synth_async(Design*, NetScope*, const NetBus&, NetBus&): Assertion `statement_default == 0' failed.

Aborted

The log file is attached on this page http://www.deorha.com/home/mtp/simply-risc. It is errorlog_2

This was also written in the synth.log file. I have also been given an idea by Ashutosh that I should try synthesizing it in centOS in a Virtual Box. That's what my agenda for today is.